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APW7065
Synchronous Buck PWM Controller
Features
* * * * * * * * * * *
Single 12V Power Supply Required Fast Transient Response - 0~90% Duty Ratio 0.8V Reference with 1% Accuracy Shutdown Function by Controlling COMP Pin Voltage Internal Soft-Start (3.4ms) Function Voltage Mode PWM Control Design Under-Voltage Protection Over-Current Protection - Sense Low Side MOSFET' RDS(ON) s 300KHz Fixed Switching Frequency SOP-8 Package Lead Free Available (RoHS Compliant)
General Description
The APW7065 uses fixed 300KHz switching frequency, voltage mode, synchronous PWM controller which drives dual N-channel MOSFETs. The device integrates the control, monitoring and protection functions into a single package, provides one controlled power output with under-voltage and over-current protections. The APW7065 provides excellent regulation for output load variation. The internal 0.8V temperaturecompensated reference voltage is designed to meet the requirement of low output voltage applications. An built-in digital soft-start with fixed soft-start interval prevents the output voltage from overshoot as well as limiting the input current. The APW7065 with excellent protection functions: POR, OCP and UVP. The Power-On Reset (POR) circuit can monitor VCC supply voltage exceeds its threshold voltage while the controller is running, and a built-in digital soft-start provides output with controlled voltage rise. The Over-Current Protection (OCP) monitors the output current by using the voltage drop across the lower MOSFET' RDS(ON), comparing with s internal VOCP (0.27V), when the output current reaches the trip point, the controller will run the soft-start function until the fault events are removed. The UnderVoltage Protection (UVP) monitors the voltage of FB pin for short-circuit protection, when the VFB is less than 50% of VREF (0.4V), the controller will shutdown the IC directly.
Applications
* *
Graphics Card Mother Board
Pinouts
BOOT UGATE GND LGATE 1 2 3 4 8 7 6 5 PHASE COMP FB VCC
SOP-8
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Feb., 2006 1 www.anpec.com.tw
APW7065
Ordering and Marking Information
APW 7065
Lead Free Code Handling Code Temp. Range Package Code APW7065 K : APW7065 XXXXX Package Code K : SOP-8 Operating Ambient Temp. Range E : -20 to 70 C Handling Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
Block Diagram
VCC GND
BOOT Power-On Reset
UGATE
Sense Low Side O.C.P Comparator 0.27V 50%VREF :2 Error Amp PWM Comparator U.V.P Comparator
Digital Soft Start
PHASE
Gate Control
LGATE
VREF Oscillator Sawtooth Wave FOSC 300KHz
FB
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COMP
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APW7065
Application Circuit
12V 1N4148 1uH 2.2R 1uF 5 1uF 470uFx2 470uF
VIN (12V)
VCC
BOOT UGATE
1 0.1uF 2 8 Q2 APM2506 Q1 APM2509 1uH
VOUT (1.2V)
Q3 2N7002 ON/OFF
PHASE
7
COMP LGATE
4
470uFx2
33nF 8.2nF 2.7K
6
FB GND
3 1K
2K
18R
68nF
Absolute Maximum Ratings
Symbol VCC BOOT UGATE LGATE PHASE COMP, FB TJ TSTG TSDR VESD VCC to GND BOOT to PHASE UGATE to PHASE LGATE to GND PHASE to GND COMP, FB to GND Junction Temperature Range Storage Temperature Maximum Soldering Temperature, 10 Seconds Minimum ESD Rating (Human Body Mode) (Note 2) <400nS pulse width >400nS pulse width <400nS pulse width >400nS pulse width <400nS pulse width >400nS pulse width Parameter Rating -0.3 ~ 16 -0.3 ~ 16 -5 ~ BOOT+5 -0.3 ~ BOOT+0.3 -5 ~ VCC+5 -0.3 ~ VCC+0.3 -5 ~ 21 -0.3 ~ 16 -0.3 ~ 7 -20 ~ 150 -65 ~ 150 300 2 Unit V V V V V V
o o o
C C C
kV
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: The device is ESD sensitive. Handling precautions are recommended.
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APW7065
Recommended Operating Conditions
Symbol VCC VOUT VIN IOUT TA TJ Parameter VCC Supply Voltage Converter Output Voltage Converter Input Voltage Converter Output Current Ambient Temperature Range Junction Temperature Range Range 10.8 ~ 13.2 0.8 ~ 5 2.9 ~ 13.2 0 ~ 20 -20 ~ 70 -20 ~ 125 Unit V V V A
o
C C
o
Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC=12V, and TA =-20~70oC. Typlcal values are at TA=25oC.
Symbol SUPPLY CURRENT IVCC VCC Nominal Supply Current VCC Shutdown Supply Current POWER-ON RESET Rising VCC Threshold Falling VCC Threshold COMP Shutdown Threshold COMP Shutdown Hysteresis OSCILLATOR FOSC VOSC VREF Free Running Frequency Ramp Amplitude Reference Voltage Accuracy ERROR AMPLIFIER Gain SR VCOMP VCOMP Open Loop Gain Slew Rate FB Input Current COMP High Voltage COMP Low Voltage RL=10k, CL=10pF(Note3) RL=10k, CL=10pF(Note3) RL=10k, CL=10pF(Note3) VFB = 0.8V(Note3) 88 15 6 0.1 5.5 0 1 dB MHz V/us uA V V GBWP Open Loop Bandwidth Measured at FB Pin TA =-20~70C -1.0 255 300 1.6 0.8 +1.0 345 kHz VP-P V % 9 7.5 9.5 8 1.2 0.1 10 8.5 V V V V UGATE and LGATE Open UGATE, LGATE = GND 5 1 10 2 mA mA Parameter Test Conditions APW7065 Min Typ Max Unit
REFERENCE VOLTAGE
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APW7065
Electrical Characteristics (Cont.)
Unless otherswise specified, these specifications apply over VCC=12V and TA =-20~70oC. Typlcal values are at TA=25oC.
Symbol Parameter Test Conditions APW7065 Min Typ 5 5 2.6 1.05 4.9 1.4 2 1.6 1.3 20 0.23 45 0.27 0.31 50 55 3 2.4 1.95 Max Unit
ERROR AMPLIFIER (Cont.) ICOMP ICOMP COMP Source Current COMP Sink Current VCOMP=2V VCOMP=2V BOOT = 12V, VUGATE -VPHASE = 2V BOOT = 12V, VUGATE -VPHASE = 2V VCC = 12V, VLGATE = 2V VCC = 12V, VLGATE = 2V BOOT = 12V, IUGATE = 0.1A BOOT = 12V, IUGATE = 0.1A VCC = 12V, ILGATE = 0.1A VCC = 12V, ILGATE = 0.1A mA mA A A A A nS V %
GATE DRIVERS IUGATE Upper Gate Source Current IUGATE Upper Gate Sink Current ILGATE ILGATE Lower Gate Source Current Lower Gate Sink Current
RUGATE Upper Gate Source Impedance RUGATE Upper Gate Sink Impedance RLGATE Lower Gate Source Impedance RLGATE Lower Gate Sink Impedance TD VOCP VUVP Dead Time PROTECTIONS
1.25 1.88
Over-Current Reference Voltage TA =-20~70C Under-Voltage Threshold Trip Point Soft-Start Interval Percent of VREF
SOFT-START TSS 2 3.4 5 ms
Note 3: Guaranteed by design.
Functional Pin Description
BOOT (Pin 1) A bootstrap circuit with a diode connected to VCC is used to create a voltage suitable to drive a logic-level N-channel MOSFET. UGATE (Pin 2) Connect this pin to the high-side N-channel MOSFET' s gate. This pin provides gate drive for the high-side MOSFET. GND (Pin 3) The GND terminal provides return path for the IC' bias s current and the low-side MOSFET driver' pull-low s current. Connect the pin to the system ground via very low impedance layout on PCBs. LGATE (Pin 4) Connect this pin to the low-side N-channel MOSFET' s gate. This pin provides gate drive for the low-side MOSFET.
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APW7065
Functional Pin Description (Cont.)
VCC (Pin 5) Connect this pin to a 12V supply voltage. This pin provides bias supply for the control circuitry and the low-side MOSFET driver. The voltage at this pin is monitored for the Power-On Reset (POR) purpose. It is recommended that a decoupling capacitor (1 to 10uF) be connected to GND for noise decoupling. FB (Pin 6) This pin is the inverting input of the internal error amplifier. Connect this pin to the output (VOUT) of the converter via an external resistor divider for closedloop operation. The output voltage set by the resistor divider is determined using the following formula :
R1 VOUT = 0.8 x 1 + R2 where R1 is the resistor connected from VOUT to FB ,
FB pin is also monitored for under voltage events. COMP (Pin 7) This pin is the output of PWM error amplifier. It is used to set the compensation components. In addition, if the pin is pulled below 1.2V, it will disable the device. PHASE (Pin 8) This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source. This pin is also used to monitor the voltage drop across the MOSFET for over-current protection.
and R2 is the resistor connected from FB to GND. The
Typical Characteristics
Power On
VCC=12V, Vin=12V Vo=1.2V, L=1uH
CH1
Power Off
CH1
VCC=12V, Vin=12V Vo=1.2V, L=1uH
CH2
CH2
CH3
CH3
CH4
CH4
CH1: VCC (5V/div) CH2: VFB (1V/div) CH3: Vo (1V/div) CH4: Ug (20/Vdiv) Time: 10ms/div
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CH1: VCC (5V/div) CH2: VFB (1V/div) CH3: Vo (1V/div) CH4: Ug (20/Vdiv) Time: 10ms/div
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APW7065
Typical Characteristics (Cont.)
EN
VCC=12V, Vin=12V Vo=1.2V, L=1uH
CH1 CH1
Shutdown
VCC=12V, Vin=12V Vo=1.2V, L=1uH
CH2
CH2
CH3
CH3
CH4
CH4
CH1: VCOMP (2V/div) CH2: Vo (1V/div) CH3: Ug (20V/div) CH4: Lg (10Vdiv) Time: 5ms/div
CH1: VCOMP (2V/div) CH2: Vo (1V/div) CH3: Ug (20V/div) CH4: Lg (10Vdiv) Time: 20us/div
UGATE Rising
VCC=12V, Vin=12V Vo=1.2V, L=1uH Iout=5A
CH1
UGATE Falling
VCC=12V, Vin=12V Vo=1.2V, L=1uH Iout=5A
CH1
CH2
CH2
CH3
CH3
CH1: Ug (20V/div) CH2: Lg (5V/div) CH3: Phase (10V/div) Time: 50ns/div
CH1: IL (10A/div) CH2: Vo (1V/div) CH3: Ug (20V/div) CH4: Lg(10V/div) Time: 100us/div
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APW7065
Typical Characteristics (Cont.)
Load Transient Response
VCC=12V, Vin=12V Vo=1.2V, L=1uH
CH1 CH1
Under Voltage Protection
VCC=12V, Vin=12V Vo=1.2V, L=4.7uH
0 10A
CH2
CH3
0A
CH2
CH4
1
CH1: Vo (500mV/div,AC) CH2:Io (5A/div) Time: 1ms/div 2
1
2
CH1: IL (10A/div) CH2: Vo (1V/div) CH3: Ug (20V/div) CH4: Lg (10V/div) Time: 100us/div
Over Current Protection
VCC=12V, Vin=12V,Vo=1.2V, L=1uH, L_side: APM2023, Rds(on)=17m[
CH1
CH1
Short Test
VCC=12V, Vin=12V Vo=1.2V, L=1uH
CH2
CH2
CH3
CH3
CH4
CH4
CH1: IL (10A/div) CH2: Vo (2V/div) CH3: Ug (20V/div) CH4: Lg (10V/div) Time: 2ms/div
CH1: IL (10A/div) CH2: Vo (2V/div) CH3: Ug (20V/div) CH4: Lg (10V/div) Time: 5ms/div
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APW7065
Typical Characteristics (Cont.)
Switching Frequency vs. Junction Temperature
310 305 300 295 290 285 280 275 -40 -20
VCC=12V
Reference Voltage vs. Junction Temperature
0.804
Switching Frequency(KHz)
0.802
VCC=12V
Reference Voltage(V)
0 20 40 60 80 100 120
0.8
0.798
0.796
0.794
0.792 -40 -20 0 20 40 60 80 100 120
Junction Temperature (C )
Junction Temperature (C )
UGATE Source Current vs. UGATE Voltage
3.5 3
UGATE Sink Current vs. UGATE Voltage
3
VBOOT=12V PHASE=2V
UGATE Source Current (A)
VBOOT=12V PHASE=2V
2.5 2 1.5 1 0.5 0 0 2 4 6 8 10 12
UGATE Sink Current (A)
2.5 2 1.5 1 0.5 0 0
2
4
6
8
10
12
UGATE Voltage (V)
UGATE Voltage (V)
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APW7065
Typical Characteristics (Cont.)
LGATE Source Current vs. LGATE Voltage
6
LGATE Sink Current vs. LGATE Voltage
3.5
LGATE Source Current (A)
LGATE Sink Current (A)
5 4
VCC=12V
3 2.5 2 1.5 1 0.5 0
VCC=12V
3 2
1 0 0 2 4 6 8 10 12
0
2
4
6
8
10
12
LGATE Voltage (V)
LGATE Voltage (V)
Functional Description
Power On Reset (POR) The Power-On Reset (POR) function of APW7065 continually monitors the input supply voltage (VCC) and the COMP pin. The supply voltage (VCC) must exceed its rising POR threshold voltage. The POR function initiates soft-start operation after VCC and COMP voltages exceed their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold. The POR function inhibits operation at disabled status (VCOMP is less than 1.2V). With both input supplies above their POR thresholds, the device initiates a soft-start interval. Soft-Start The APW7065 has a built-in digital soft-start to control the output voltage rise and limit the current surge during the start-up. In Figure 1, when VCC exceeds rising POR threshold voltage, it will delay 2048/Fosc
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Feb., 2006 10
seconds and then begin soft start. During soft-start, an internal ramp connected to the one of the positive inputs of the Gm amplifier rises up from 0V to 2V to replace the reference voltage (0.8V) until the ramp voltage reaches the reference voltage. The soft-start interval is decided by the oscillator frequency (300kHz). The formulation is given by:
Tdelay = t 2 - t 1 = 2048/FOSC = 6.8ms
Tsoft-start = t 3 - t 2 = 1024/F = 3.4ms OSC Figure 2. shows more detail of the FB voltage ramp. The FB voltage soft-start ramp is formed with many small steps of voltage. The voltage of one step is about 12.5mV in FB, and the period of one step is about 16/ FOSC. This method provides a controlled voltage rise
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APW7065
Functional Description (Cont.)
Soft-Start (Cont.) and prevents the large peak current to charge output capacitor.
Voltage(V)
- The MOSFET' RDS(ON) is varied by temperature and s gate to source voltage, the user should determine the maximum RDS(ON) in manufacturer' s datasheet. - The minimum Vocset should be used in the above equation. - Note that the ILIMIT is the current flow through the lower MOSFET; ILIMIT must be greater than maximum output current add the half of inductor ripple current. Shutdown and Enable
VCC
V OUT
t1
t2 t3
Time
Figure 1.
Voltage(V) FB
Pulling the COMP voltage to GND by an open drain transistor, shown in typical application circuit, shutdown the APW7065 PWM controller. In shutdown mode, the UGATE and LGATE turn off and pull to PHASE and GND respectively. Under Voltage Protection
12.5mV
16/Fosc
Time
Figure 2. Over-Current Protection The over-current protection monitors the output current by using the voltage drop across the lower MOSFET' s RDS(ON) and this voltage drop will be compared with the internal 0.27V reference voltage. If the voltage drop across the lower MOSFET' RDS(ON) is larger than s 0.27V, an over-current condition is detected. The threshold of the over current limit is given by:
ILimit = 0.27 R DS( ON)
The FB pin is monitored during converter operation by the internal Under Voltage (UV) comparator. If the FB voltage drops below 50% of the reference voltage (50% of 0.8V = 0.4V), a fault signal is internally generated, and the device turns off both high-side and low-side MOSFET and the converter' output is latched to be s floating.
Application Information
Output Voltage Selection The output voltage can be programmed with a resistive divider. Use 1% or better resistors for the resistive divider is recommended. The FB pin is the inverter input of the error amplifier, and the reference voltage is 0.8V. The output voltage is determined by:
R V OUT = 0.8 x 1 + OUT R GND
For the over-current is never occurred in the normal operating load range; the variation of all parameters in the above equation should be determined.
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Where ROUT is the resistor connected from V OUT to FB and RGND is the resistor connected from FB to GND.
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APW7065
Application Information (Cont.)
Output Inductor Selection The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor value reduces the inductor' ripple current and s induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by:
IRIPPLE = VIN - VOUT V x OUT FS x L VIN
capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1uF can be connected between the drain of upper MOSFET and the source of lower MOSFET. MOSFET Selection The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum output current requirement. There are two components of loss in the MOSFETs: conduction loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the following: PUPPER = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS PLOWER = IOUT (1+ TC)(RDS(ON))(1-D) Where I OUT is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction loss while the upper MOSFET include an additional transition loss. The switching internal, tSW, is a function of the reverse transfer capacitance CRSS. The (1+TC) term is
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VOUT = IRIPPLE x ESR
where FS is the switching frequency of the regulator. Although increase of the inductor value reduces the ripple current and voltage, a tradeoff will exist between the inductor' ripple current and the regulator load s transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage. Output Capacitor Selection Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is intended for switching regulator applications. In some applications, multiple capacitors have to be parallel to achieve the desired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. If tantalum
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APW7065
Application Information (Cont.)
MOSFET Selection (Cont.) to factor in the temperature dependency of the RDS(ON) and can be extracted from the "RDS(ON) vs Temperature" curve of the power MOSFET. PWM Compensation The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain slope and 180 degrees phase shift in the control loop. A compensation network among COMP, FB and VOUT should be added. The compensation network is shown in Fig. 6. The output LC filter consists of the output inductor and output capacitors. The transfer function of the LC filter is given by:
FLC -40dB/dec GAIN (dB)
FESR -20dB/dec
Frequency(Hz)
Figure 4. The LC Filter GAIN and Frequency The PWM modulator is shown in Figure 5. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given by: VIN GAIN PWM = VOSC
VIN OSC GVOSC Driver PWM Comparator PHASE
GAIN
LC
=
1 + s x ESR x C OUT s 2 x L x C OUT + s x ESR x C OUT + 1
The poles and zero of this transfer functions are: 1 FLC = 2 x x L x C OUT
FESR = 1 2 x x ESR x C OUT
Output of Error Amplifier Driver
The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor.
PHASE L OUTPUT
Figure 5. The PWM Modulator The compensation network is shown in Figure 6. It provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by:
1 1 // R2 + sC1 sC2 = GAIN AMP 1 R1// R3 + sC3 1 1 s + x s + R2 x C2 (R1 + R3 ) x C3 R1 + R3 = x C1 + C2 1 R1 x R3 x C1 s s + x s + R2 x C1 x C2 R3 x C3 V = COMP V OUT
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COUT ESR
Figure 3. The Output LC Filter
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APW7065
Application Information (Cont.)
PWM Compensation (Cont.) The poles and zeros of the transfer function are:
F Z1 = 1 2 x x R2 x C2
F Z2 =
FP1 =
1 2 x x (R1 + R3 ) x C3
1 C1 x C2 2 x x R2 x C1 + C2
Calculate the C2 by the equation: 1 C2 = 2 x x R2 x FLC x 0.75 4.Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the equation: C2 C1 = 2 x x R2 x C2 x FESR - 1 5.Set the second pole FP2 at the half of the switching frequency and also set the second zero F Z2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the error amplifier.
FP2
1 = 2 x x R3 x C3
C1 R3 C3 R2 C2
VOUT R1 FB VREF VCOMP
FP2 = 0.5 X FO FZ2 = FLC Combine the two equations will get the following component calculations: R1 R3 = FS -1 2 x FLC 1 C3 = x R3 x FS
Figure 6. Compensation Network The closed loop gain of the converter can be written as: GAINLC X GAINPWM X GAINAMP Figure 7. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. 1.Choose a value for R1, usually between 1K and 5K. 2.Select the desired zero crossover frequency F O: (1/5 ~ 1/10) X F S >FO>FESR Use the following equation to calculate R2:
FZ1 FZ2
FP1
FP2
GAIN (dB)
20log (R2/R1)
20log (VIN/GVOSC)
Compensation Gain
VOSC FO R2 = x x R1 VIN FLC
3.Place the first zero FZ1 before the output LC filter double pole frequency F LC. FZ1 = 0.75 X FLC
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FLC FESR PWM & Filter Gain Frequency(Hz) Converter Gain
Figure 7. Converter Gain and Frequency
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APW7065
Application Information (Cont.)
Layout Considerations In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at 300KHz, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short, wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. And signal and power grounds are to be kept separate till combined using ground plane construction or single point grounding. Figure 8. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: - Keep the switching nodes (UGATE, LGATE and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UG, LG) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component,
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the resistor dividers, and boot capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). - The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. - The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking.
APW7065 VCC BOOT UGATE PHASE LGATE
VIN
L O A D
VOUT
Figure 8.Layout Guidelines
APW7065
Package Information
SOP-8 pin (Reference JEDEC Registration MS-012)
E
H
e1
e2
D
A1
A
1
0.015X45
L 0.004max.
Dim A A1 D E H L e1 e2 1
Millimeters Min. 1.35 0.10 4.80 3.80 5.80 0.40 0.33 1.27BSC 0 8 0 Max. 1.75 0.25 5.00 4.00 6.20 1.27 0.51 Min. 0.053 0.004 0.189 0.150 0.228 0.016 0.013
Inches Max. 0.069 0.010 0.197 0.157 0.244 0.050 0.020 0.50BSC 8
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APW7065
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone T L to T P
Ramp-up
Temperature
TL Tsmax
tL
Tsmin Ramp-down ts Preheat
25
t 25 C to Peak
Time
Classificatin Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (T L) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds
6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Feb., 2006 17 www.anpec.com.tw
APW7065
Classification Reflow Profiles (Cont.)
Table 1. SnPb Entectic Process - Package Peak Reflow Temperature s Package Thickness V o l u m e m m3 Volume mm 3 <350 350 <2.5 mm 240 +0/-5C 225 +0/-5C 2.5 mm 225 +0/-5C 225 +0/-5C
Table 2. Pb-free Process - Package Classification Reflow Temperatures Package Thickness Volume mm3 Volume mm3 Volume mm3 <350 350-2000 >2000 <1.6 mm 260 +0C * 260 +0 C * 260 +0C * 1.6 mm - 2.5 mm 260 +0C * 250 +0 C * 245 +0C * 2.5 mm 250 +0C * 245 +0 C * 245 +0C * *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0 C. For example 260C+0C) at the rated MSL level.
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 SEC 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 100mA
Carrier Tape & Reel Dimensions
t P P1 D
Po E
F W
Bo
Ao
Ko D1
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Feb., 2006
18
www.anpec.com.tw
APW7065
Carrier Tape & Reel Dimensions (Cont.)
T2
J C A B
T1
Reel Dimensions
Application A 330 1 SOP- 8 F 5.5 1 B C J 2 0.5 Po T1 12.4 0.2 P1 T2 2 0.2 Ao W 12 0. 3 Bo P 8 0.1 Ko E 1.750.1 t 62 +1.5 12.75+ 0.15 D D1
1.55 +0.1 1.55+ 0.25 4.0 0.1
2.0 0.1 6.4 0.1
5.2 0. 1 2.1 0.1 0.30.013
(mm)
Cover Tape Dimensions
Application SOP- 8 Carrier Width 12 Cover Tape Width 9.3 Devices Per Reel 2500
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Feb., 2006
19
www.anpec.com.tw

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